DocumentCode
2432776
Title
Power and noise aware test using preliminary estimation
Author
Noda, Kenji ; Ito, Hideaki ; Hatayama, Kazumi ; Aikyo, Takashi
Author_Institution
Semicond. Technol. Acad. Res. Center, Yokohama, Japan
fYear
2009
fDate
28-30 April 2009
Firstpage
323
Lastpage
326
Abstract
Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.
Keywords
automatic test pattern generation; boundary scan testing; design for testability; ATPG; DFT; IR-drop; clock cycle; noise aware scan test method; power aware scan test method; power consumption; preliminary estimation; Automatic test pattern generation; Circuit testing; Delay effects; Energy consumption; Flip-flops; Logic testing; Noise reduction; Semiconductor device noise; Semiconductor device testing; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-2781-9
Electronic_ISBN
978-1-4244-2782-6
Type
conf
DOI
10.1109/VDAT.2009.5158160
Filename
5158160
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