DocumentCode
2432927
Title
A case study on MPEG4 decoder design with SystemBuilder
Author
Shibata, Seiya ; Honda, Shinya ; Tomiyama, Hiroyuki ; Takada, Hiroaki
Author_Institution
Grad. Sch. of Inf. Sci., Nagoya Univ., Nagoya, Japan
fYear
2009
fDate
28-30 April 2009
Firstpage
355
Lastpage
358
Abstract
This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named system builder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the behavioral description based on the analysis result obtained by a profiler. Finally, we achieve over 15 fps performance with pipelined hardware implementation.
Keywords
codecs; field programmable gate arrays; logic design; video coding; FPGA; MPEG4 decoder design; pipelined hardware implementation; system builder; system-level design toolkit; Computer architecture; Decoding; Embedded system; Field programmable gate arrays; Hardware; High level synthesis; MPEG 4 Standard; Superluminescent diodes; System-level design; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-2781-9
Electronic_ISBN
978-1-4244-2782-6
Type
conf
DOI
10.1109/VDAT.2009.5158168
Filename
5158168
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