An efficient hardware implementation for interpolating and decimating filters

In this age of 40-microcent transistors, it is easy to become complacent about the consumption of resources. Easy, that is, until your design no longer fits in the desired target device. This paper revisits techniques for multirate, multichannel filter design that were used from the mid-1970s through the 1980s and applies them by using contemporary development tools and hardware. It demonstrates a 7:1 reduction in hardware resources over intellectual property (IP) supplied by field programmable gate array (FPGA) vendors.