DocumentCode
2433440
Title
Embedded testing for data communications circuits
Author
Lin, San ; Mourad, Samiha
Author_Institution
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
Volume
2
fYear
2002
fDate
2002
Firstpage
467
Abstract
This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed testing of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 μm CMOS implementation is expected in early 2002.
Keywords
CMOS integrated circuits; IEEE standards; built-in self test; data communication equipment; embedded systems; integrated circuit testing; transceivers; 0.35 micron; 400 Mbit/s; BIST methodology; at-speed testing; data communications chip; data communications circuits; embedded testing; functional blocks; functional testing; silicon CMOS implementation; three-port IEEE 1394a system; transceivers; Added delay; Built-in self-test; Circuit testing; Clocks; Data communication; Decoding; Delay systems; Jitter; Logic testing; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN
0-7803-7596-3
Type
conf
DOI
10.1109/ICECS.2002.1046198
Filename
1046198
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