Design of multiplierless FIR filters with an adder depth versus filter order trade-off

In this work, the trade-offs in FIR filter design are studied. This includes the adder depth for the constant filter coefficients, the number of adders, and the number of delay elements, i.e., the filter order. It is shown that the proposed design algorithm can be used to decrease both the overall arithmetic complexity and the adder depth, possibly with a small penalty in delay elements. This is achieved by selecting coefficients that can be realized at a lower depth, i.e., the lengths of the logic paths are reduced. Hence, this directly translates into decreased power consumption due to reduced glitch propagation and increased throughput due to a shorter critical path.