DocumentCode
2433591
Title
Design and FPGA implementation an accurate real time 3×4 MIMO channel emulator
Author
Nasr, Omar A. ; Daneshrad, Babak
fYear
2009
fDate
1-4 Nov. 2009
Firstpage
764
Lastpage
768
Abstract
The design and implementation of an accurate and low complexity MIMO channel emulator is presented in this paper. A mathematical analysis is used to verify the accuracy of the emulator over a wide range of SNRs (0 - 35 dBs). The complexity of the emulator is reduced by preprocessing of the channels and hardward/software partitioning. All 802.11n channel models can be emulated on our platform. A 3×4 10MHz version of the emulator is successfully running on a Virtex-II XC2V6000-4 FPGA. A 20MHz version was synthesized and simulated on an XC2V6000-6 FPGA.
Keywords
MIMO communication; field programmable gate arrays; mathematical analysis; telecommunication channels; wireless LAN; SNR; Virtex-II XC2V6000-4 FPGA; channels preprocessing; frequency 10 MHz; frequency 20 MHz; hardware partitioning; mathematical analysis; real time MIMO channel emulator; software partitioning; Field programmable gate arrays; MIMO;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2009 Conference Record of the Forty-Third Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
978-1-4244-5825-7
Type
conf
DOI
10.1109/ACSSC.2009.5469958
Filename
5469958
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