Performance optimization of dynamic CMOS circuits through transistor sizing

One of the predominately used circuit styles in high-performance VLSI systems is dynamic CMOS due to its advantage in speed. However, the rising magnitude of circuits implemented on a chip, along with shrinking device size and process variations have increased the complexity of implementing dynamic CMOS circuit efficiently. Answering this challenge, this paper proposes a performance optimization technique for dynamic CMOS circuits that operates based on a Schmitt Trigger and pseudo pMOS feedback keeper. When implemented using IBM 90nm CMOS process, the proposed optimization technique has shown an improvement in worst-case delay by 44.84%, delay uncertainty by 55%, delay sensitivity by 34%, and power consumption by 36% when compared to their initial performances.