Mapping of the FFT on a reconfigurable architecture targeted to SDR applications

Author

Garzia, Fabio ; Airoldi, Roberto ; Nurmi, Jari ; Giliberto, Carmela ; Brunelli, Claudio

Author_Institution

Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland

fYear

2009

fDate

5-7 Oct. 2009

Firstpage

157

Lastpage

160

Abstract

This paper describes the implementation of a FFT on a system based on a GP core and a reconfigurable coarse-grain accelerator. The entire system has been prototyped on an Altera Stratix II device. On the prototype a 1024-point FFT gives a 40X speed-up in comparison with the software implementation. The 1024-point FFT is executed in 400 mubeta. Considering an ASIC synthesis of the coarse-grain array, the 1024-point FFT is executed in 42 mubeta, against the 104 mubeta of a DSP implementation.

Keywords

application specific integrated circuits; fast Fourier transforms; reconfigurable architectures; software radio; ASIC synthesis; Altera Stratix II device; DSP implementation; FFT mapping; SDR applications; coarse-grain array; fast Fourier transform; reconfigurable architecture; reconfigurable coarse-grain accelerator; software defined radio; software implementation; Application software; Bandwidth; Hardware; Memory management; Multiaccess communication; OFDM; Paper technology; Reconfigurable architectures; Software prototyping; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2009. SOC 2009. International Symposium on

Conference_Location

Tampere

Print_ISBN

978-1-4244-4465-6

Electronic_ISBN

978-1-4244-4467-0

Type

conf

DOI

10.1109/SOCC.2009.5335655

Filename

5335655