DocumentCode
2434067
Title
An efficient algorithm for gate matrix compactions
Author
Hou, Cliff Yungchin ; Chen, C. Y Roger
Author_Institution
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
fYear
1989
fDate
22-24 March 1989
Firstpage
533
Lastpage
537
Abstract
The authors present an efficient algorithm to minimize the layout area by taking the physical sizes of each line, variable net spacing, contact offset, diffusion line offset, and metal line offset into consideration. This algorithm can be used as a postprocessing step for the gate matrix layout. Significant reduction in the layout area, compared to results without performing layout compaction, is achieved.<>
Keywords
circuit layout CAD; contact offset; diffusion line offset; efficient algorithm; gate matrix compactions; layout area; metal line offset; minimisation; postprocessing step; variable net spacing; Circuits; Compaction; Contacts; Fabrication; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Communications, 1989. Conference Proceedings., Eighth Annual International Phoenix Conference on
Conference_Location
Scottsdale, AZ, USA
Print_ISBN
0-8186-1918-x
Type
conf
DOI
10.1109/PCCC.1989.37441
Filename
37441
Link To Document