DocumentCode
2434296
Title
Performance modeling of parallel applications on MPSoCs
Author
Lattuada, Marco ; Pilato, Christian ; Tumeo, Antonino ; Ferrandi, Fabrizio
Author_Institution
Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
fYear
2009
fDate
5-7 Oct. 2009
Abstract
In this paper we present a new technique for automatically measuring the performance of tasks, functions or arbitrary parts of a program on a multiprocessor embedded system. The technique instruments the tasks described by OpenMP, used to represent the task parallelism, while ad hoc pragmas in the source indicate other pieces of code to profile. The annotations and the instrumentation are completely target-independent, so the same code can be measured on different target architectures, on simulators or on prototypes. We validate the approach on a single and on a dual LEON 3 platform synthesized on FPGA, demonstrating a low instrumentation overhead. We show how the information obtained with this technique can be easily exploited in a hardware/software design space exploration tool, by estimating, with good accuracy, the speed-up of a parallel application given the profiling on the single processor prototype.
Keywords
embedded systems; field programmable gate arrays; hardware-software codesign; logic design; multiprocessing systems; system-on-chip; FPGA; MPSoC design; OpenMP; ad hoc pragmas; dual LEON 3 platform; hardware-software design; multiprocessor embedded system; performance modeling; single processor prototype; task parallelism; Application software; Computer architecture; Embedded system; Field programmable gate arrays; Hardware; Instruments; Software design; Software prototyping; Space exploration; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2009. SOC 2009. International Symposium on
Conference_Location
Tampere
Print_ISBN
978-1-4244-4465-6
Electronic_ISBN
978-1-4244-4467-0
Type
conf
DOI
10.1109/SOCC.2009.5335675
Filename
5335675
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