Development and comparison of reduced-order interconnect macromodels for time-domain simulation

As signal speeds grow and feature sizes shrink in digital VLSI circuits, there is an increasing need to correctly model the interconnects between transistors. Since the size of the resulting RLC-interconnect network can be huge, model-reduction algorithms have been developed for replacing the RLC networks with reduced-order frequency-domain models. This paper focuses on interfacing these frequency-domain representations with the time-domain simulation of the original nonlinear circuit. Three well-known reduced-order macromodels are briefly reviewed and two new ones are proposed. Comparisons between the simulation times and memory consumption of the various models are presented.