6-T SRAM using dual threshold voltage transistors and low-power quenchers

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output bit lines of memories caused by large currents in the bit lines is reduced by adding two back-to-back quenchers between them. The proposed quenchers not only prevent the oscillation, but also reduce the idle power consumption when the memory cells are not activated by the wordline signal. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAM is feasible.