DocumentCode
2435395
Title
A 2.0 GHz 4 Mb pseudo-SRAM with on-chip BIST for refresh in 0.18u CMOS technology with LVDS output data bus drivers
Author
Bathaee, Mehdi ; Mostoufi, Zed ; Ghezelayagh, Hamid ; Afkham, Anahita
Author_Institution
LSI Design & Integration Corp., San Jose, CA, USA
Volume
2
fYear
2002
fDate
2002
Firstpage
839
Abstract
This paper presents a novel design solution of a high-speed memory in a normal 0.18 μm CMOS-technology. Different solutions are used to reduce read data errors and noise effects.
Keywords
CMOS memory circuits; SRAM chips; built-in self test; driver circuits; integrated circuit design; integrated circuit noise; integrated circuit reliability; logic design; low-power electronics; system buses; 0.18 micron; 2.0 GHz; 4 Mbit; CMOS pseudo-SRAM; LVDS output data bus drivers; high-speed memory; noise effect reduction; on-chip BIST refresh; read data error reduction; Adaptive control; Built-in self-test; CMOS technology; Circuits; Condition monitoring; Differential amplifiers; Logic; Noise reduction; Programmable control; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN
0-7803-7596-3
Type
conf
DOI
10.1109/ICECS.2002.1046306
Filename
1046306
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