High density 3D silicon interposer technology development and electrical characterization for high end applications

As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer approach combined with 3D integration technologies opens new possibilities in advanced packaging. Especially for high end applications where several processor needs to communicate together, this approach could enhance the performances of whole systems. However there are many requirements for this type of packaging as: — Thin wafer processing for silicon interposer, -High I/O density between chips and silicon interposer, -Compatibility with CTE mismatch between organic substrate and large silicon interposer. In the first part of this paper the design of the silicon interposer demonstrator successfully processed will be presented as well as the integration schemes with chip and organic substrate. Then, the process flow developed for this application will be commented in order to explain the main technological levels. A dedicated part will focus on silicon interposer bow optimization which is one of the most critical point for mounting. Finally, the electrical performances of each level and of combined chains will be presented and analyzed with some preliminary results of mounting with chips and organic substrate.