Title :
Thermal-stress analysis of SOIC packages and interconnections
Author :
Lau, John H. ; Harkins, Girvin
Author_Institution :
Hewlett-Packard Lab., Palo Alto, CA, USA
Abstract :
Thermal stresses in surface-mounted small-outline integrated-circuit (SOIC) assemblies are studied using the finite-element method. Emphasis is placed on the effects of solder-joint geometry on package and interconnection reliability. In addition, the problem of voids in solder joints is addressed. Seven different solder-joint geometries and six different void sizes are considered. It is found that the voids in the solder joint increase the stresses acting on it. The results presented can provide guidelines for solder joint inspection.<>
Keywords :
finite element analysis; inspection; reliability; soldering; surface mount technology; SMT; SOIC packages; finite-element method; guidelines; interconnections; reliability; small-outline integrated-circuit; solder joint inspection; solder-joint geometry; stresses; thermal stress analysis; void sizes; voids in solder joints; Assembly; Electronic packaging thermal management; Electronics packaging; Geometry; Integrated circuit interconnections; Lead; Residual stresses; Soldering; Surface-mount technology; Thermal stresses;
Conference_Titel :
Electronics Components Conference, 1988., Proceedings of the 38th
Conference_Location :
Los Angeles, CA, USA
DOI :
10.1109/ECC.1988.12565
