Research and Implementation of a High-Speed Reconfigurable A5 Algorithm

A high-speed and dynamic reconfigurable hardware architecture of A5 algorithm is presented, which can satisfy the different characteristic of A5/1 and A5/2 algorithm. To save the hardware cost and get shorter critical path, we proposed reconfigurable clock controlling unit and output function, which can be reconfigured to realize the critical function of two algorithms. As to the different high-speed method, the paper performs detailed comparison and analysis. The design has been realized using Altera´s FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18 mum CMOS process, the result proves the critical throughput rate can achieve 880 Mbps.