Title :
Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness
Author :
Chieh-Yang Chen ; Wen-Tsung Huang ; Yiming Li
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. By using a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFETs. The resist-LER is most influential on characteristic fluctuation. For the same type, spacer-LER has at least 85 % improvement on σVth compared with resist-LER. As for the digital circuit characteristic, the rectangle-shape bulk FinFET has larger timing fluctuation.
Keywords :
Gaussian noise; MOSFET; digital circuits; power consumption; 3D quantum-mechanically-corrected device simulation; DC/AC; FinFET; digital circuit; electrical characteristic; line edge roughness; power consumption; size 14 nm; time-domain Gaussian noise function; Capacitance; Digital circuits; FinFETs; Fluctuations; Logic gates; Power demand; Timing; Line edge roughness; digital circuit; fin-; gateLER; resist-; sidewall-; spacer-; trapezoidal bulk FinFET;
Conference_Titel :
Quality Electronic Design (ISQED), 2015 16th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-7580-8
DOI :
10.1109/ISQED.2015.7085399