Title :
Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins
Author :
Ker, Ming-Dou ; Chung-Yu Wu ; Cheng, Tao ; Wu, Chung-Yu ; Yu, T.-L. ; Wang, Alex C.
Author_Institution :
Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification
Keywords :
CMOS integrated circuits; ULSI; VLSI; electrostatic discharge; failure analysis; integrated circuit reliability; integrated circuit technology; protection; CMOS ICs; CMOS ULSI; CMOS VLSI; ESD failure; multiple power pins; whole-chip ESD protection; CMOS integrated circuits; CMOS technology; Electrostatic discharge; Pins; Power system protection; Robustness; Stress; Ultra large scale integration; Variable structure systems; Very large scale integration;
Conference_Titel :
Integrated Reliability Workshop, 1994. Final Report., 1994 International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-1908-7
DOI :
10.1109/IRWS.1994.515839
