Study of the impact of aging on many-core energy-efficient DSP systems

During the normal operational use, integrated circuits go through what is popularly known as wearout or aging. At system level, aging causes gradual speed degradation of the design over their service life. In a many-core homogeneous design and over a period of activity, this can lead to variation in speed depending on the workload distribution on cores. In the same design context, Voltage Scaling (VS) is another very widely used technique in gaining energy-efficiency. Process Variation (PV) also tend to have similar impact creating variation in speed and power among the cores. In this paper, we will first study the impact of aging and PV on above design system. Further, we will analyze their impact on energy efficient configurations under static and dynamic workload environment. Later, we will present our analysis over two different usage policies; using fastest core on the die as compared to uniform aging of all cores in the system. We conclude, that using fastest core in the system will yield higher performance benefits over its lifetime.