On designing digit multipliers

The folding and unfolding techniques cannot be used to design pipelined digit adders because of the presence of feedback loops. In this paper, approaches for the design of digit multipliers that can be pipelined to the bit level are presented. It includes architectures obtained via unfolding, the high radix approach and the multi-pipe approach. The pipelining of these architectures has been made possible thanks to a new "pipelined digit adder". The presented architectures are scalable, systolic and can offer a great flexibility in finding the best trade-off between hardware cost and throughput rate by changing the level of pipelining and the digit size.