• DocumentCode
    2437613
  • Title

    A register allocation technique using register existence graph

  • Author

    Koseki, A. ; Komastu, H. ; Fukazawa, Y.

  • Author_Institution
    Sch. of Sci. & Eng., Waseda Univ., Tokyo, Japan
  • fYear
    1997
  • fDate
    11-15 Aug 1997
  • Firstpage
    404
  • Lastpage
    411
  • Abstract
    Optimizing compilation is very important for generating code sequences in order to utilize the characteristics of processor architectures. One of the most essential optimization techniques is register allocation. In register allocation that takes account of instruction-level parallelism, anti-dependences generated when the same register is allocated to different variables, and spill code generated when the number of registers is insufficient should be handled in such a way that the parallelism in a program is not lost. In our method, we realized register allocation using a new data structure called the register existence graph, in which the parallelism in program is well expressed
  • Keywords
    data structures; instruction sets; optimising compilers; parallelising compilers; code sequences; data structure; instruction-level parallelism; optimizing compilation; processor architectures; register allocation technique; register existence graph; Interference; Laboratories; Parallel processing; Program processors; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing, 1997., Proceedings of the 1997 International Conference on
  • Conference_Location
    Bloomington, IL
  • ISSN
    0190-3918
  • Print_ISBN
    0-8186-8108-X
  • Type

    conf

  • DOI
    10.1109/ICPP.1997.622673
  • Filename
    622673