Optimized concurrent interleaving architecture for high-throughput turbo-decoding

Future applications of turbo-codes will demand higher throughput than the currently envisioned 2 Mbit/s for 3rd generation wireless communication. Several approaches have already been made to design high throughput component decoders. The interleavers which separate the component decoders, however, have not yet gained much attention, although they form a severe data transfer bottleneck. Based on our previous work, which demonstrated how to widen the interleaver bottleneck through concurrent interleaving, we present in this paper a new architecture optimized with respect to routing and interconnect properties of deep-submicron technologies. Our interconnect driven design approach leads to simplified local interleaver cells with almost negligible control flow. No global routing nor global control is necessary. A parameterizable VHDL model was developed for profiling and synthesis under the 3GPP scenario using different degrees of parallelization.