Novel integrated development environment for implementing PLC on FPGA by converting ladder diagram to synthesizable VHDL code

Programmable logic controllers (PLCs) are the universally accepted automation components in industrial control. IEC61131-3 standard was developed to unify textual and graphical ways of describing the control specification for PLCs; ladder diagram being one such control specifications. However, PLCs available in the market as on today are vendor specific and replacement of PLC of one vendor in a process equipment by PLC of another vendor is not possible due to lack of standardization among EDA tools from PLC vendors. Secondly, heart of PLCs is a sequential processor which cannot execute parallel rungs of ladder diagram concurrently. Perhaps this aspect did not pose any problem so far due to large response times associated with industrial processes. However with introduction of high speed MEMS sensors along with increased control complexity, the need for high speed PLCs has been spelt out. Further, the safety features of control system are now expected to be integral part of ladder control specification. Field Programmable Gate Arrays (FPGAs) have better portability support, ability to support implementation of concurrent logic and security aspects. They have been mentioned in the literature as prospective programmable devices to implement control logic of PLCs. However, utilization of FPGAs for implementing control specification demands development of integrated environment to convert ladder logic as per IEC61131-3 to HDL. This HDL specification further can be ported to any of the standard FPGA development environments. It is seen through literature that not enough efforts have been focused on developing such integrated environment. This paper focuses on the details of such environment being developed by authors to convert IEC-61131-3 control specification standard to VHDL for direct synthesis.