Title :
An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor
Author :
Wu, David M. ; Lin, Mike ; Reddy, Madhukar ; Jaber, Talal ; Sabbavarapu, Anil ; Thatcher, Larry
Abstract :
This work describes an optimized DFT architecture and its implementation strategy for an Intel high performance (>3 GHz) microprocessor. Major DFT features and ATPG techniques implemented are described and key results are presented to show the return-on-investments (ROI) in the high volume manufacturing (HVM) test environments.
Keywords :
automatic test pattern generation; design for testability; integrated circuit design; integrated circuit testing; microprocessor chips; ATPG techniques; DFT architecture; Intel high performance microprocessor; high volume manufacturing test environment; return on investment; test pattern generation; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Design for disassembly; Design for testability; Logic testing; Microprocessors; Silicon; Test pattern generators;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1386935
