Modeling the output waveform of CMOS gate with feedback effect

Author

Yang, Li ; Yuan, J.S. ; Hagedorn, M.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL, USA

Volume

3

fYear

2002

fDate

2002

Firstpage

1127

Abstract

Modeling of the output waveform of a CMOS gate with feedback is presented. A decoupling technique for strong-coupled components is proposed to reduce such a complex gate to a unidirectional structure, which can be further simplified to an equivalent inverter. Short-channel effects, sub-threshold currents, and non-linear characteristics of MOS transistors, in the triode region, are accounted for. The proposed method is employed to solve the hysteresis of an NCL (NULL convention logic) threshold gate (K.M. Fant and S.A. Brandt, US Patent #5,305,463, Apr. 1994). The results are validated by SPICE simulation. This approach can be incorporated in the existing equivalent-inverter technique for fast timing simulations.

Keywords

CMOS logic circuits; MOSFET; SPICE; circuit feedback; circuit simulation; equivalent circuits; hysteresis; integrated circuit design; integrated circuit modelling; logic CAD; logic gates; logic simulation; semiconductor device models; timing; MOS transistor triode region nonlinear characteristics; NCL threshold gate hysteresis; NULL convention logic; SPICE simulation; complex gate reduction; equivalent circuits; equivalent inverters; fast timing applications; short-channel effects; strong-coupled component decoupling techniques; sub-threshold currents; unidirectional gate structure; CMOS logic circuits; Circuit simulation; Computational modeling; Feedback loop; Inverters; MOSFETs; Output feedback; Parasitic capacitance; SPICE; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046450

Filename

1046450