Efficient static D-latch standard cell characterization using a novel setup time model

In this paper we propose a simple setup time model for a transmission gate based static latch, which we later use to simplify standard cell library characterization methodology. We propose a simple model for the setup time which relates it linearly with input transition time (T_R) and load capacitance (C_L). We also derive the region of validity of our model in the T_R, C_L space. We derive the relationship of the model coefficients and the model´s region of validity with the size of CMOS latch standard cell. We then derive simple expressions relating our model coefficients with the supply voltage, threshold voltage, and temperature variations. We use these relationships to simplify latch setup time characterization methodology, eliminating the necessity of about 67% HSPICE simulations. We show that our model and method of improving the characterization process are valid with the technology scaling and realistic input signals. We observe that the value of setup time obtained using our model based approach for latch characterization differ from their corresponding HSPICE based method by a maximum (average) of 3.2% (1.5%).