DocumentCode :
2438207
Title :
Interconnect test pattern generation algorithm for meeting device and global SSO limits with safe initial vectors
Author :
Baker, Kendrick ; Nourani, Mehrdad
Author_Institution :
Raytheon Co., Plano, TX, USA
fYear :
2004
fDate :
26-28 Oct. 2004
Firstpage :
163
Lastpage :
172
Abstract :
This work presents a method of creating a true/complement pattern set of optimal size that satisfies simultaneous switching limit constraints. This method is an improvement over previous methods in that it has better runtime characteristics as well as the ability to handle additional scenarios. It can produce safe initial vectors, produce vectors that consider switching limits by device rather than globally, and reduce (or eliminate) the number of morph vectors required.
Keywords :
automatic test pattern generation; binomial distribution; boundary scan testing; integrated circuit interconnections; integrated circuit testing; logic testing; binomial distribution; boundary scan testing; interconnect test pattern generation algorithm; logic testing; morph vectors elimination; morph vectors reduction; safe initial vectors; simultaneous switching output limit; switching limit constraints; true-complement pattern set; Circuit faults; Integrated circuit interconnections; Interference; Logic devices; Runtime; Signal design; Switches; Switching circuits; Test pattern generators; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
Type :
conf
DOI :
10.1109/TEST.2004.1386949
Filename :
1386949
Link To Document :
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