• DocumentCode
    2438285
  • Title

    Non-deterministic DUT behavior during functional testing of high speed serial busses: challenges and solutions

  • Author

    Hops, Jonathan ; Swing, Brian ; Phelps, Brian ; Sudweeks, Bruce ; Pane, John ; Kinslow, James

  • Author_Institution
    Semicond. Test, Teradyne Inc., Boston, MA, USA
  • fYear
    2004
  • fDate
    26-28 Oct. 2004
  • Firstpage
    190
  • Lastpage
    196
  • Abstract
    The characteristics defining non-determinism for PCI Express busses are explored. The RapidIO® bus is used as a point of comparison. ATE architecture is proposed to significantly reduce the yield and throughput impact of random output. A specific architecture is explored and proposed for real-time pass/fail analysis of HSS data streams in the ATE environment.
  • Keywords
    automatic test equipment; high-speed integrated circuits; integrated circuit testing; peripheral interfaces; ATE architecture; PCI Express busses; RapidIO® bus; functional testing; high speed serial busses; nondeterministic DUT behavior; real time pass-fail analysis; Clocks; Out of order; Payloads; Physical layer; Production; Protocols; Semiconductor device testing; Semiconductor devices; Throughput; Transmitters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2004. Proceedings. ITC 2004. International
  • Print_ISBN
    0-7803-8580-2
  • Type

    conf

  • DOI
    10.1109/TEST.2004.1386952
  • Filename
    1386952
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2438285