DocumentCode :
243850
Title :
A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing
Author :
Bose, Anjan ; Ghosal, P. ; Mohanty, S.P.
Author_Institution :
Indian Inst. of Eng. Sci. & Technol., Howrah, India
fYear :
2014
fDate :
9-11 July 2014
Firstpage :
136
Lastpage :
141
Abstract :
Due to the limitations of traditional bus based systems, Network-on-Chip (NoC) has evolved as the most dominanttechnology in the paradigm of communication-centric revolution, where, besides the computation, inter-communication between the cores is an indispensable aspect of a SoC. Furthermore, the emergence of three dimensional integrated circuits (3D-ICs) has resulted in better performance, functionality, and packaging density compared to traditional planar ICs. The amalgamation of these two technologies, the 3D NoC architecture, can combine the benefits of these two new domains to offer an unprecedentedperformance gain. In this paper, we present a new 3D topological NoC design based on the butterfly fat tree (BFT) topology with an efficient table based uniform routing algorithm for 3D NoC. Extensive simulation experiments have been performed for BFT and compared to mesh, torus, butterfly and flattened butterfly topologies against four performance metrics viz. overall average latency, overall average acceptance rate, overall minimum acceptance rate, and average hop counts. There are significant latency improvements of 43-89 %, 83-88 %, 46-96 %, and 31-95 % over other topologies respectively. Average hop count is improved by 30 % and 13 % over mesh and torus. Also, there are improvements in average acceptance rate and minimum acceptance rate of 1-8 % and 5-14 % respectively for flattened butterfly and 6-9 % and 6-13 % over torus. Results evidently show that BFT is a very good choice for low network latency and faster communication.
Keywords :
integrated circuit design; network routing; network-on-chip; three-dimensional integrated circuits; 3D topological NoC design; butterfly fat tree topology; flattened butterfly topology; low latency scalable 3D NoC; mesh topology; network-on-chip; table based uniform routing; three dimensional integrated circuits; torus topology; Computer architecture; IP networks; Network topology; Routing; System-on-chip; Three-dimensional displays; Topology; 3D Network on Chip; Low Network Latency; NoC Architecture; Table Based Routing; Uniform Hopping Distance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
Type :
conf
DOI :
10.1109/ISVLSI.2014.51
Filename :
6903349
Link To Document :
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