DocumentCode :
243876
Title :
On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties
Author :
Mitra, Rajendu ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Author_Institution :
Dept. of Comput. Sci. & Eng., Jadavpur Univ., Kolkata, India
fYear :
2014
fDate :
9-11 July 2014
Firstpage :
202
Lastpage :
207
Abstract :
Although path-delay faults (PDF) have been studied extensively during the last three decades, design of combinational circuits to achieve low-overhead robust PDF testability, still poses many challenges. In this paper, we revisit the problem of synthesizing a robust path-delay fault testable combinational circuit based on certain new functional properties. Given the boolean cubes of a function, we first design a two-level robust PDF testable circuit by properly grouping the cubes using a few additional control lines. Next, we apply some testability-preserving algebraic factorization techniques to design multi-level circuits. The method readily extends to multi-output circuits as well. Experimental results establish that the proposed functional approach yields fully robust PDF-testable circuits with much lower overhead as compared to earlier approaches.
Keywords :
Boolean functions; combinational circuits; design for testability; integrated circuit design; integrated circuit testing; Boolean cubes; algebraic factorization techniques; design-for-testability; multilevel circuits; multioutput circuits; robust path-delay fault testable combinational circuits; two-level robust PDF testable circuit; Circuit faults; Combinational circuits; Delays; Discrete Fourier transforms; Integrated circuit modeling; Robustness; Silicon; Boolean cubes; design-for-testability; path-delay fault; robust test;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
Type :
conf
DOI :
10.1109/ISVLSI.2014.81
Filename :
6903360
Link To Document :
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