A speed enhancing architecture for a floating point signal processor

In contrast to fixed-point arithmetic, floating-point arithmetic requires more steps for a given operation, which normally slows down the execution speed of a floating-point processor. A special hardware architecture for minimizing this problem is proposed. The processor is a four-address machine with Harvard architecture. A two-level pipelining is introduced., i.e. fetching of operands and storing of the result are done in parallel with arithmetic calculations. This pipelining is invisible for the programmer, because a special register allows the access to the result of the last operation. The fundamental arithmetic operation is D=A+B*C.Addressing of operands is either direct or indexed with base offset and auto-modification. All of these addressing modes can be used independently for all of the four addresses in one instruction