Channel masking synthesis for efficient on-chip test compression

Author

Chickermane, Vivek ; Foutz, Brian ; Keller, Brion

Author_Institution

Cadence Design Syst., Endicott, NY, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

452

Lastpage

461

Abstract

The effectiveness of on-product test compression methods is degraded by the capture of unknown logic states ("X-states") by the scan elements. This work describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow. Results are presented to show its effectiveness on some large industrial designs.

Keywords

automatic test pattern generation; built-in self test; integrated circuit design; integrated circuit testing; logic testing; system-on-chip; automatic test pattern generation; channel masking hardware; channel masking synthesis; large industrial designs; on-chip test compression; product test compression methods; scan elements; typical design flow; unknown logic states; Automatic test pattern generation; Automatic testing; Circuit testing; Delay; Logic design; Logic testing; Read-write memory; System testing; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1386981

Filename

1386981