Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET)

This paper presents the concept of a new field effect transistor (FET) based on ferroelectric insulator. The proposed design is a Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material with the design of a partially depleted silicon-on-insulator (PDSOI) device. In this structure we propose to develop a negative capacitance (NC) in the body of the device by utilizing the inherent hysteresis behavior of ferroelectric material, which would be inserted as a buried insulator layer in between silicon substrate and a thin buffer layer in a PDSOI device structure. In addition to introduce the concept of a new ferroelectric insulator based SOI device structure, this paper presents closed form models to calculate the subthreshold swing of the proposed device. It is demonstrated that by carefully optimizing the thickness of the ferroelectric film, dielectric property of the insulator, and the channel thickness, the device can be operated at a subthreshold swing below 60mV/decade that represent the theoretical thermodynamic limit of conventional MOSFET performance.