Fault tolerant arithmetic with applications in nanotechnology based systems

Several emerging nanotechnologies have been displaying the negative differential resistance (NDR) characteristic, which makes them naturally support multi-valued logic with a large number of logic states. Such multi-valued logic with a large number of logic states can support a native digit-level redundant number system and hence a native digit-level carry save arithmetic. We present a new approach to linear block code based fault-tolerant arithmetic in NDR nanotechnologies. Specifically, we show how linear block codes can be used for error checking and error correction in carry save arithmetic operations. The proposed approach significantly improves timing and fault-tolerance of arithmetic operations in the highly unreliable nanoelectronic environment. Since digit-level information redundancy via linear block codes is widely used for fault tolerant communications and storage systems, the proposed scheme also unifies the fault tolerance approaches across arithmetic, interconnection and storage subsystems.