A Formal Method for Rapid SoC Prototyping

In this paper a formal method is proposed, based on attribute grammars (AG), for rapid SoC prototyping. A generic platform is also proposed for the automatic SoC implementation of AG-based applications. The proposed system, given the specification of the application in the formalism of attribute grammars, automatically produces the necessary hardware modules for the syntactic and semantic analysis of input strings belonging to that grammar. The produced implementation tackles with the recognition task of the input string, using a hardware implementation of an extension of Earley´s parallel parsing algorithm. Moreover, the system exhibits capabilities of inexactness. The attribute evaluation makes usage of a stack-based hardware. The hardware modules are described in Verilog Hardware Description Language (Verilog HDL) and synthesizedin a Xilinx Virtex-5 ML506 FPGA. For the illustration of the proposed system, an example from the area of hardware compilers is given.