DocumentCode
2439077
Title
An economic analysis and ROI model for nanometer test
Author
Keller, Bnon ; Tegethoff, Mick ; Bartenstein, Thomas ; Chickermane, Vivek
Author_Institution
Cadence Design Syst. Inc., Endicott, NY, USA
fYear
2004
fDate
26-28 Oct. 2004
Firstpage
518
Lastpage
524
Abstract
This work describes an economic and return-on-investment (RoI) model for a test methodology that ensures product quality for logic devices that are in the 130 nm technology node and below. We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition to ensuring product quality we address the cost of test and time to volume and how both factors can be improved. Examples from realistic scenarios are provided to illustrate the net savings from the proposed NTM using this model.
Keywords
integrated circuit economics; integrated circuit testing; integrated logic circuits; investment; logic testing; nanoelectronics; 130 nm; economic analysis; integrated circuit testing; logic devices; nanometer test; product quality; return on investment model; test methodology; Circuit faults; Circuit testing; Costs; Delay effects; Frequency; Geometry; Leakage current; Logic devices; Manufacturing; Semiconductor device testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN
0-7803-8580-2
Type
conf
DOI
10.1109/TEST.2004.1386988
Filename
1386988
Link To Document