Toward Holistic Modeling, Margining and Tolerance of IC Variability

The 2013 edition of the International Technology Roadmap for Semiconductors [10] highlights a slowdown of traditional pitch and density scaling in leading-edge patterning technologies. Through the foundry N5/N7 nodes, the roadmap also projects unfavorable scaling of device and interconnect electrical performance (drive vs. leakage, resistivity, capacitive coupling, etc.). IC product value is also challenged by increasingly dominant variability mechanisms ranging from lithography and planarization in manufacturing, to dynamic voltage droop and aging in the field. Design teams compensate variability with margin (guardbanding), but this substantially reduces the value of designs at the next technology node. In this context, it is increasingly critical to deliver design-based equivalent scaling through novel design technologies. This paper reviews recent research directions that seek to improve modeling, margining and tolerance of IC variability. Collectively, these design methods offer new means by which product companies can extract greater value from available technologies, even as traditional scaling slows for patterning, devices and interconnects.