Improving GA-Based NoC Mapping Algorithms Using a Formal Model

Network on Chip (NoC) is a sophisticated communication infrastructure that provides quality of service (QoS) guarantees for a complex Systems-on-Chip (SoC) application. Some applications demand guaranteed end-to-end latency. Mapping algorithms are used to map an application on an NoC to satisfy the bandwidth constraints and end-to-end latency requirements. The design of the mapping algorithms determines their capability in reaching a near optimal or optimal solution. Genetic algorithms (GA) based NoC mapping algorithms are increasingly used for mapping. They search the mapping space efficiently using a cost function to estimate a performance parameter that represents the "cost" associated with the solution, in this case latency. Generally analytical models are used to estimate cost, however, analytical models are not able to accurately estimate worst-case end-to-end latency. Motivated by this, we are proposing to use a formal NoC model to accurately estimate end-to-end latency, and incorporate it into GA cost function. The capability of the proposed method to find a near optimal or optimal solution is demonstrated with sample applications.