DocumentCode :
243931
Title :
Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN
Author :
Ziesemer, Adriel M. ; Reis, R.
Author_Institution :
Inst. Fed. do Rio Grande do Sul (IFRS), Canoas, Brazil
fYear :
2014
fDate :
9-11 July 2014
Firstpage :
350
Lastpage :
355
Abstract :
This paper describes a technique to compact cell layouts efficiently using Mixed-Integer Linear Programming. By using binary variables we were able not only to model the conditional design rules, which apply to technology nodes down to 65nm, but also to compact layouts in the two-dimensions simultaneously. This technique was applied to a transistor network layout synthesis tool called ASTRAN which is being used to generate on-demand cells with unrestricted transistor network structure. We demonstrate in this paper that our technique is able to generate dense cell layouts, competitive with manually designed cells.
Keywords :
integer programming; integrated circuit layout; linear programming; ASTRAN; MILP; binary variables; mixed-integer linear programming; transistor network layout synthesis tool; two-dimensional cell layout compaction; Compaction; Layout; Libraries; Logic gates; Metals; Routing; Transistors; 2-D; EDA; MILP; cell synthesis; layout compaction; two-dimensional;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
Type :
conf
DOI :
10.1109/ISVLSI.2014.79
Filename :
6903388
Link To Document :
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