• DocumentCode
    2439363
  • Title

    Decision selection and learning for an ´all-solutions ATPG engine´

  • Author

    Chandrasekar, Kameshwar ; Hsiao, Michael S.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
  • fYear
    2004
  • fDate
    26-28 Oct. 2004
  • Firstpage
    607
  • Lastpage
    616
  • Abstract
    ´All-solutions ATPG´ based methods have found applications in model checking sequential circuits, and they can also improve the defect coverage of a test-suite, by generating distinct multiple-detect patterns. Conventional decision selection heuristics and learning techniques for an ATPG engine were originally developed to ´quickly´ find any available (single) solution. Such decision selection heuristics may not be the best for an ´all-solutions ATPG´ engine, where all the solutions need to be found. In this paper, we explore new techniques to guide an ´all-solutions ATPG engine´. We first present a new decision selection heuristic that makes use of the ´connectivity of gates´ in the circuit in order to obtain a compact solution-set. Next, we analyze the ´symmetry in search-states´ that was exploited in ´success-driven learning´ and extend it to prune conflict sub-spaces as well. Finally, we propose a new metric that determines the use of learnt information a priori. This information is stored and used efficiently during ´success driven learning´. Experimental results show that we can compute the complete solution-set with our new heuristics for large ISCAS´89 and ITC´99 circuits, where conventional guidance heuristics fail.
  • Keywords
    automatic test pattern generation; decision making; sequential circuits; ISCAS89 circuits; ITC99 circuits; all-solutions ATPG based methods; all-solutions ATPG engine; decision selection heuristics; model checking sequential circuits; multiple detect patterns; success driven learning; Automatic test pattern generation; Boolean functions; Circuit faults; Circuit testing; Data structures; Engines; Explosions; Message-oriented middleware; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2004. Proceedings. ITC 2004. International
  • Print_ISBN
    0-7803-8580-2
  • Type

    conf

  • DOI
    10.1109/TEST.2004.1386998
  • Filename
    1386998