DocumentCode
2439444
Title
Localizing open interconnect defects using targeted routing in FPGA´s
Author
Mark, Dave ; Fan, Jenny
fYear
2004
fDate
26-28 Oct. 2004
Firstpage
627
Lastpage
634
Abstract
A break though test strategy for detecting and localizing open metal interconnects faults is described in this paper. It utilizes the reprogrammable nature of FPGA ´s to quickly isolate metal defects on different individual metal interconnect layers with existing FPGA resources. By only programming the FPGA once, multiple defects are isolated for each physical metal layer. Experimental results from a low yield wafer verified this methodology by successfully identifying the physical defect locations. The experimental results are presented in this paper. This strategy can also be applied to detecting metal bridging defects.
Keywords
fault location; field programmable gate arrays; logic testing; network routing; FPGA; logic testing; metal bridging defect detection; metal defect isolation; metal interconnect layers; open interconnect defect localization; open metal interconnects fault detection; open metal interconnects fault localization; physical defect location; targeted routing; Circuit faults; Circuit testing; Failure analysis; Fault detection; Field programmable gate arrays; Integrated circuit interconnections; Logic testing; Random access memory; Routing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN
0-7803-8580-2
Type
conf
DOI
10.1109/TEST.2004.1387000
Filename
1387000
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