Title :
Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis
Author :
Gaillardon, Pierre-Emmanuel ; Amaru, Luca Gaetano ; De Micheli, G.
Author_Institution :
EPFL, Lausanne, Switzerland
Abstract :
For more than four decades, Complementary Metal-Oxide-Semiconductor (CMOS) Field Effect Transistors (FETs) have been the baseline technology for implementing digital computation systems. CMOS transistors natively implement Not-AND (NAND)- and Not-OR (NOR)-based logic operators. Nowadays, we observe a trend towards devices with an increased set of logic capabilities, i.e., with the ability to realize in a compact way specific logic operators as compared to the standard CMOS. In particular, controllable-polarity devices enable a native and compact realization of eXclusive-OR (XOR)- and MAJority (MAJ)- logic functions, and open a large panel of opportunities for future high-performance computing systems. However, main current logic synthesis tools exploit algorithms using NAND/NOR representations that are not able to fully exploit the capabilities of novel XOR- and MAJ-oriented technologies. In this paper, we review some recent work that aims at providing novel logic synthesis techniques that natively assess the logic capabilities of XOR- and MAJ-operators.
Keywords :
VLSI; binary decision diagrams; field effect transistors; logic design; logic gates; network synthesis; NAND/NOR representations; and-or-inverter graph; biconditional binary decision diagram; controllable-polarity transistors; exclusive-OR logic functions; field effect transistors; logic synthesis tools; majority logic functions; majority-inverter graph; Boolean functions; CMOS integrated circuits; Data structures; Field effect transistors; Logic gates; Silicon; Nanowire transistors; exclusive or (XOR); logic synthesis; majority (MAJ); polarity control;
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
DOI :
10.1109/ISVLSI.2014.107