Parallel implementation of fractal image compression

Author

Uys, R.F.

Author_Institution

Dept. of Electron. Eng., Natal Univ., Durban, South Africa

fYear

1998

fDate

7-8 Sep 1998

Firstpage

143

Lastpage

148

Abstract

This paper presents an implementation of fractal image compression on a Texas Instruments TMS320C80 parallel processor chip. The work focuses on improving encoding speed. Speed gains are nearly linearly related to the number of processors used. An approach for reducing the number of calculations made, based on the variance of pixel values over sub-blocks of the image is presented. The various techniques employed allow a 512×512 pixel 256 grey-level image to be compressed in under 20 seconds, while maintaining peak signal to noise ratios of close to 30 dB. This paper also describes an extension of this work to allow colour images to be compressed

Keywords

data compression; digital signal processing chips; fractals; image coding; image colour analysis; parallel architectures; TMS320C80 parallel processor chip; Texas Instruments; colour image compression; encoding speed; fractal image compression; grey-level image; parallel implementation; peak signal to noise ratios; pixel values; Colored noise; Decoding; Digital signal processing; Fractals; Image coding; Image converters; Instruments; Iterative algorithms; PSNR; Pixel;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Signal Processing, 1998. COMSIG '98. Proceedings of the 1998 South African Symposium on

Conference_Location

Rondebosch

Print_ISBN

0-7803-5054-5

Type

conf

DOI

10.1109/COMSIG.1998.736938

Filename

736938