• DocumentCode
    243971
  • Title

    Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing

  • Author

    Kanoun, Karama ; Ruggiero, Matteo ; Atienza, David ; Van der Schaar, Mihaela

  • Author_Institution
    Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
  • fYear
    2014
  • fDate
    9-11 July 2014
  • Firstpage
    468
  • Lastpage
    473
  • Abstract
    In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. In this context, stream mining applications are now widely used in several domains such as financial analysis, video annotation, surveillance, medical services, traffic prediction, etc. In order to cope with the Big-Data stream input and its high variability, modern stream mining applications implement systems with heterogeneous classifiers and adapt online to its input data stream characteristics variation. Moreover, unlike existing architectures for video processing and compression applications, where the processing units are reconfigurable in terms of parameters and possibly even functions as the input data is changing, in Big-Data stream mining applications the complete computing pipeline is changing, as entirely new classifiers and processing functions are invoked depending on the input stream. As a result, new approaches of reconfigurable hardware platform architectures are needed to handle Big-Data streams. However, hardware solutions that have been proposed so far for stream mining applications either target high performance computing without any power consideration (i.e., limiting their applicability in small-scale computing infrastructures or current embedded systems), or they are simply dedicated to a specific learning algorithm (i.e., limited to run with a single type of classifiers). Therefore, in this paper we propose a novel low-power many-core architecture for stream mining applications that is able to cope with the dynamic data-driven nature of stream mining applications while consuming limited power. Our exploration indicates that this new proposed architecture is able to adapt to different classifiers complexities thanks to its multiple scalable vector processing units and their re-configurability feature at run-time. Moreover, our platform archite- ture includes a memory hierarchy optimized for Big-Data streaming and implements modern fine-grained power management techniques over all the different types of cores allowing then minimum energy consumption for each type of executed classifier.
  • Keywords
    Big Data; data mining; low-power electronics; memory architecture; multiprocessing systems; parallel processing; pattern classification; power aware computing; reconfigurable architectures; Big-Data stream computing; Big-Data stream handling; Big-Data stream mining applications; energy consumption minimisation; fine-grained power management techniques; heterogeneous classifiers; hidden patterns; high performance computing; input data stream characteristics variation; learning algorithm; low power many-core architecture; memory hierarchy; multiple scalable vector processing units; processing functions; reconfigurable hardware platform architectures; scalable many-core architecture; Buffer storage; Data mining; Graphics processing units; Hardware; Memory management; Streaming media; Big-Data; Low-Power; Many-core; Memory Hierarchy; Online; Reconfigurable; Stream Mining Application; Streaming application;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Tampa, FL
  • Print_ISBN
    978-1-4799-3763-9
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2014.77
  • Filename
    6903408