Glitch Power Reduction via Clock Skew Scheduling

Dynamic power consumption is directly related tothe number of the signal transitions in a circuit. Glitches are undesired spurious transitions caused by inputs of a gate arriving at different times, instead of arriving together, thus causing unnecessary power dissipation. Our objective in this paper is to reduce the number of glitches in a circuit to reduce dynamic power. We do so by clock skew scheduling, where different flipflopsreceive clocks at different times. We formulate thescheduling as an Integer linear Programming problem andderive vector-independent clock skew schedule to reduce glitches. We also propose linear objective functions based on timing window of gates for optimization. The proposed method was evaluated on ISCAS-89 benchmark circuits using dynamic simulation. Results show that we achieve an average reduction of ~32% in glitch power.