On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery

The Intrinsic capacitance of CMOS circuits provides inexpensive decoupling capacitance for power supply noise mitigation. In FinFET circuits, such capacitance has greater dependence on the logic states of gates. Consequently, when a group of gates are inactive, there exists a combination of inputs that will maximize the decoupling capacitance for the power supply. In this paper, (i) we establish the input dependence of decoupling capacitance in FinFET circuits based on simulation results and (ii) propose a pattern generation solution to find an input pattern that maximizes such capacitance. This analysis is potentially important for circuit initialization in sleep states and in design planning for power delivery networks. The exact pattern generation problem is known to be computationally intractable. To reduce the order of computation, we propose simplification to the state dependent capacitance model that preserves accuracy while greatly reducing the amount of computation. The pattern generation problem is formulated as an Integer Linear Programming (ILP) problem. We evaluate the proposed solution on ISCAS-85 benchmark circuits. This approach is shown to be superior than random pattern simulation based solution. The scalability of the solution is improved via constraint-objective model order reduction and modeling at a higher level.