Acyclic circuit partitioning for path delay fault emulation

Summary form only given. Acyclic partitioning of VLSI circuits is studied under area/delay, 1-0 size and communication constraints. In this paper, we define the path-delay-fault emulation problem which adds a new constraint, viz. path count constraint, to partitioning problem. We present two algorithms to solve the problem. The first algorithm decomposes a circuit into entirely-fanout-free cones (EFFC), and clusters them into partitions. The second one finds an intermediate partitioning solution with the partitioning algorithm ignoring path count constraint. Later, it applies the first algorithm to the partitions which violate the path count constraint. We implemented the first algorithm and measured its efficiency in terms of the number of resulting partitions, cut-cost, and time cost for ISCAS85 benchmarks.