An efficient design of embedded memories and their testability analysis using Markov chains

A design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM), where the address, read/write, and data input lines are not directly controllable and the data output lines are not externally observable, is presented. Unlike conventional approaches which use a linear feedback shift register (LFSR) to generate a signature and a register to store the reference fault-free signature, this technique uses a testable design which both accelerates the test by a factor of 0.5√n in an n-bit RAM and improves the test reliability by eliminating the LFSR. The problem of memory initialization has been elegantly circumvented by using word-line flag registers. An in-depth and comprehensive analysis of the functional faults, such as stuck-at, coupling, and pattern-sensitive, is performed. The analysis shows that, in order to test a 1-Mb RAM for common functional faults, the technique needs only 1 s, as opposed to about an hour needed by the conventional random testing