Processor Design with Asymmetric Reliability

Continuous shrinking of device size has introduced reliability as a new design challenge for embedded processors. Error mitigation techniques trade off reliability for other design metrics such as performance and power consumption. State-of-the-art fault-tolerant designs involve cross-layer error management, which lead to an over-protected system. To address the overhead issue, asymmetric reliability utilizes unequal protection levels for different system components based on various criticality requirements. In this paper, We propose a versatile asymmetric error detection/correction framework based on instruction-level vulnerability analysis. Inspired from information-theoretic view of processor as a noisy network, asymmetric error correction coding schemes are designed and exploited to efficiently trade off reliability for other performance constraints. Multiple novel asymmetric fault-tolerant design techniques are proposed, which are evaluated through a range of experiments.