Title :
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning
Author :
Ahmad, Tariq Bashir ; Ciesielski, Maciej
Author_Institution :
ECE Dept., UMASS Amherst, Amherst, MA, USA
Abstract :
While multi-core computing has become pervasive, scaling single core computations to multi-core computations remains a challenge. This paper aims to accelerate RTL and functional gate-level simulation in the current multi-core computing environment. This work addresses two types of partitioning schemes for multi-core simulation: functional, and domain-based. We discuss the limitations of functional partitioning, offered by new commercial multi-core simulators to speedup functional gate-level simulations. We also present a novel solution to increase RTL and functional gate-level simulation performance based on domain partitioning. This is the first known work that improves simulation performance by leveraging open source technology against commercial simulators.
Keywords :
hardware description languages; logic partitioning; logic simulation; multiprocessing systems; parallel processing; performance evaluation; RTL simulation; domain partitioning; functional gate-level simulation; functional partitioning; multicore computing; open source technology; parallel multicore Verilog HDL simulation; pervasive computing; simulation performance improvement; Computational modeling; Data models; Hardware design languages; Integrated circuit modeling; Logic gates; Multicore processing; Parallel processing; ASIC; Gate-level; Multi-core; Opencores; RTL; Simulation; Verilog;
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
DOI :
10.1109/ISVLSI.2014.47
